The present invention relates to a method of analyzing a semiconductor device formed on a semiconductor substrate. The invention has particular applicability in analyzing junction profiles of semiconductor devices.
The measurement of junction depth of semiconductor devices is important for the design process. Transistor design is based on modeling and/or mathematical equations. These equations are based on physical properties, such as junction depth, or behavior. Historically, junction staining for one dimensional analysis was typically done by angle lapping and then staining the junction and measuring it. The staining process comprises applying a chemical etchant which will preferentially attack n+doped material or p+doped material, allowing the technician to delineate the location of the junction and measure its depth, etc.
Two dimensional junction depth measurement is necessary when submicron features are being formed, because many two dimensional electric field effects need to be accounted for. Various prior art chemical staining and Auger spectroscopy techniques have been used, but have definite limitations for submicron gate feature transistors.
Auger spectroscopy has xe2x80x9cspot sizexe2x80x9d limitations and cannot deal with two-dimensional junction profiling. Auger spectroscopy is a form of scanning electron microscopy that analyzes spectra (i.e., energy) emitted from a surface, based on the principle that the energy emitted from a surface is indicative of the constituent material of the surface. The Auger equipment typically has a spot size of about one micron diameter and affects a depth typically several atoms or molecules thick. Thus, it cannot resolve the two dimensional junction profile of a junction depth smaller than one micron. This is problematic since junction depths are routinely on the order of one tenth of a micron. Auger spectroscopy has been successfully used for gross junction profiling where the specimen is angle lapped to yield accurate one dimensional information. However, it is not useful for performing two dimensional analysis.
Chemical staining is disadvantageous in that staining cannot be done in a depletion region since there are no free carriers. Thus, the depletion region edge does not coincide with the chemical junction edge. The chemical stain, which is an electrochemical activity, does not stain up to the junction. Therefore, actual junction depth cannot be measured, and erroneous results always occur. Furthermore, the longer the chemical etches the specimen, the deeper the junction becomes. In other words, the test affects the junction depth which is the object of measurement. Still further, the repeatability of this technique can be easily compromised if there is an error in the staining process.
Another problem with chemical staining relates to the fact that the stain is chemical doping, and the device operates because of activated doping. Thus, after chemical staining, doping is present that is not electrically active. Consequently, correct results cannot be achieved without performing additional, electrical measurements. Moreover, chemical staining does not reveal relative doping concentration, which is an extremely important parameter in transistor design. It will only detect the presence or absence of a dopant.
There exists a need for an effective methodology for accurately performing two dimensional junction profiling.
An advantage of the present invention is a method of obtaining an accurate image of a two-dimensional junction profile of a semiconductor device.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of inspecting a semiconductor device, the method comprising cross-sectioning the device to expose an active region to be inspected; imposing a direct current (DC) potential on the active region; imposing an alternating current (AC) potential on the DC potential; and scanning the active region with a scanning voltage micrograph (SVM) having an AC signal detector probe to generate an image of the active region.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.